Topological Realization of Circuits

Topological Realization of Circuits

Published by: Lucy

On: 08 Nop, 2017

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The design of integrated circuits differs from the design of board -level circuit in the importance of the actual physical realization of the active elements and interconnections that must be topologically related to each other. This requires the ...

The design of integrated circuits differs from the design of board -level circuit in the importance of the actual physical realization of the active elements and interconnections that must be topologically related to each other. This requires the interaction of the device physics, process technology constraints, and topological constraints. In order to obtain a practical solution to this complex interactive design environtment, it is generally accepted practise to describe the process constraints in the form of a design rule package. This design rule packeage is a simple description of the lateral spatial relationship of the various active-element forming geometris as well as the wiring. A simple example of design rules is shown in Fig. 13. The original concept of the design was governed by the constraints  of the technology only. However, the design data base for the geometrical description of the circuit for VLSI circuits is very large, and some constraints that limit the size of this data base have been introduced into the design rules. This is simply a quantization of the minimum spatial distance describing any technology  constraints. This kind of quantization is equivalent to the definition of the finest grid on which a geometry must fall.

There are two mayor approaches to the realization of the geometrical data base from an IC. The first is the classical approach i which the complete drawing of each individual section is introduced in to the data base in detail. This is a tedious and inefficien way of generating data. The preferred approach to data entry is through a symbolic description of the layput in which the definitions of the often-used elements are built into the system and the designer calls up such elements and strings them together on graphic entry system. These symbols are a modified description of the circuit element must like the drawing of a classical circuit schematic (Fig. 14). The design rules are than used to generate automatically the full two-dimensional geometrical description from the symbolic description. The symbolic layout system is very effisient and suffers only from a 10-20% reduction of the packing density of circuit elements compared to a detailed customized input of the complete geometries. In an attempt to reduce this gaps, software compaction of the design data base has been developed. The connection of geometries on a layout database is another aspect of intregrated circuit design that has been traditionally inefficient. Automatic wire-routing softwaredeveloped for multi-layered printed circuits boards has been adapted for this purpose and is beaing used. The use of artificial intellegence concepts in the realization of more effisient routing algoritms is under investigation.

Once the design data base has been created, the design task is to verify the validity of the data base geometrically and electrically. The geometric verification is a checking of all geometries for design rule violations. This is achieved routinely by all layout systems through software analysis of the data base. The electrical validity of the geometrical data base involves teh exaction of the electrical circuit schematic and the comparison of the electrical schematic to the various levels of hierarchy in of crusial importance to the design cycle and requires the design and geometric data bases to be compatible. It si curently common practice to extract electrical schematics and parasitic resitences and capacitances from the layout data base. The comparison occurs at the transistor level.

Various integrated design systems with the above functions are currently available.

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